Verification components:

Verification tools:


CFS-vision it's an open source project, dedicated to building software specifically for RTL verification industry. It is relying mostly on developing 'e' code for IUS simulator from Cadence as this, so far, proves to be the best solution for functional verification of integrated circuits. CFS-vision does not ignore system verilog which is catching up fast lately and promises in the near feature a release of a system verilog verification component.


 The latest release from the CFS-vision project is the eChart eVC. This application will allow one to draw charts dirrectly from the verification environment. It is a java-e tool with an easy-to-use API in both languages. It can be easily modified and extended to much of the user needs.


An other available verification component is an extremely easy to use and well documented APB eVC which should cover even the most exigent requests for this protocol.


Also, for aiding the process of building your own eVC, CFS-vision is releasing a java based eVC generator which can be used to generate the entire frame for the most used eVC architectures. For those of you out there sick and tired of command line, text interface scripts, we got good news: we have graphical interface :)


We hope you will enjoy using our products, which we are constantly developing and please keep in mind that we rely on your help for improvement by sending us your feedback!


Thank you!

© CFS - All rights reserved